////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: L.33
//  \   \         Application: netgen
//  /   /         Filename: clock_generator_synthesis.v
// /___/   /\     Timestamp: Fri Apr 02 20:44:06 2010
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim clock_generator.ngc clock_generator_synthesis.v 
// Device	: xc3s500e-5-fg320
// Input file	: clock_generator.ngc
// Output file	: F:\Tesis\FPGA\netgen\synthesis\clock_generator_synthesis.v
// # of Modules	: 1
// Design Name	: clock_generator
// Xilinx        : C:\Xilinx\11.1\ISE
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module clock_generator (
  clock8, reset, clock_in, clock50, clk16, clock_PS1, clock_PS2, clock_PS3
);
  output clock8;
  input reset;
  input clock_in;
  output clock50;
  output clk16;
  output clock_PS1;
  output clock_PS2;
  output clock_PS3;
  wire CLK8;
  wire CLK8_input;
  wire N0;
  wire PS1;
  wire PS1_input;
  wire PS2;
  wire PS3;
  wire clk16_OBUF_8;
  wire \clock16_generator/CLKFX_BUF ;
  wire clock50_OBUF_11;
  wire clock8_OBUF_13;
  wire clock_PS1_OBUF_15;
  wire clock_PS2_OBUF_17;
  wire clock_PS3_OBUF_19;
  wire clock_locked;
  wire reset_IBUF_23;
  wire \NLW_clock16_generator/DCM_SP_INST_CLK0_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_CLK90_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_CLK180_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_CLK270_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_CLK2X_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_CLK2X180_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_CLKDV_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_CLKFX180_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_PSDONE_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_STATUS<7>_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_STATUS<6>_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_STATUS<5>_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_STATUS<4>_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_STATUS<3>_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_STATUS<2>_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_STATUS<1>_UNCONNECTED ;
  wire \NLW_clock16_generator/DCM_SP_INST_STATUS<0>_UNCONNECTED ;
  GND   XST_GND (
    .G(N0)
  );
  FDCE #(
    .INIT ( 1'b0 ))
  CLOCK8_FF (
    .C(clk16_OBUF_8),
    .CE(clock_locked),
    .CLR(reset_IBUF_23),
    .D(CLK8_input),
    .Q(CLK8)
  );
  FDCE #(
    .INIT ( 1'b0 ))
  PS1_FF (
    .C(CLK8),
    .CE(clock_locked),
    .CLR(reset_IBUF_23),
    .D(PS1_input),
    .Q(PS1)
  );
  FDCE #(
    .INIT ( 1'b0 ))
  PS2_FF (
    .C(CLK8),
    .CE(clock_locked),
    .CLR(reset_IBUF_23),
    .D(PS1),
    .Q(PS2)
  );
  FDCE #(
    .INIT ( 1'b0 ))
  PS3_FF (
    .C(CLK8),
    .CE(clock_locked),
    .CLR(reset_IBUF_23),
    .D(PS2),
    .Q(PS3)
  );
  BUFG   CLK8_BUFG_INST (
    .I(CLK8),
    .O(clock8_OBUF_13)
  );
  BUFG   PS1_BUFG_INST (
    .I(PS1),
    .O(clock_PS1_OBUF_15)
  );
  BUFG   PS2_BUFG_INST (
    .I(PS2),
    .O(clock_PS2_OBUF_17)
  );
  BUFG   PS3_BUFG_INST (
    .I(PS3),
    .O(clock_PS3_OBUF_19)
  );
  DCM_SP #(
    .CLKDV_DIVIDE ( 2.000000 ),
    .CLKFX_DIVIDE ( 25 ),
    .CLKFX_MULTIPLY ( 8 ),
    .CLKIN_DIVIDE_BY_2 ( "FALSE" ),
    .CLKIN_PERIOD ( 20.0000000000000000 ),
    .CLKOUT_PHASE_SHIFT ( "NONE" ),
    .CLK_FEEDBACK ( "NONE" ),
    .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ),
    .DFS_FREQUENCY_MODE ( "LOW" ),
    .DLL_FREQUENCY_MODE ( "LOW" ),
    .DSS_MODE ( "NONE" ),
    .DUTY_CYCLE_CORRECTION ( "TRUE" ),
    .PHASE_SHIFT ( 0 ),
    .STARTUP_WAIT ( "FALSE" ))
  \clock16_generator/DCM_SP_INST  (
    .CLKIN(clock50_OBUF_11),
    .CLKFB(N0),
    .RST(reset_IBUF_23),
    .DSSEN(N0),
    .PSINCDEC(N0),
    .PSEN(N0),
    .PSCLK(N0),
    .CLK0(\NLW_clock16_generator/DCM_SP_INST_CLK0_UNCONNECTED ),
    .CLK90(\NLW_clock16_generator/DCM_SP_INST_CLK90_UNCONNECTED ),
    .CLK180(\NLW_clock16_generator/DCM_SP_INST_CLK180_UNCONNECTED ),
    .CLK270(\NLW_clock16_generator/DCM_SP_INST_CLK270_UNCONNECTED ),
    .CLK2X(\NLW_clock16_generator/DCM_SP_INST_CLK2X_UNCONNECTED ),
    .CLK2X180(\NLW_clock16_generator/DCM_SP_INST_CLK2X180_UNCONNECTED ),
    .CLKDV(\NLW_clock16_generator/DCM_SP_INST_CLKDV_UNCONNECTED ),
    .CLKFX(\clock16_generator/CLKFX_BUF ),
    .CLKFX180(\NLW_clock16_generator/DCM_SP_INST_CLKFX180_UNCONNECTED ),
    .LOCKED(clock_locked),
    .PSDONE(\NLW_clock16_generator/DCM_SP_INST_PSDONE_UNCONNECTED ),
    .STATUS({\NLW_clock16_generator/DCM_SP_INST_STATUS<7>_UNCONNECTED , \NLW_clock16_generator/DCM_SP_INST_STATUS<6>_UNCONNECTED , 
\NLW_clock16_generator/DCM_SP_INST_STATUS<5>_UNCONNECTED , \NLW_clock16_generator/DCM_SP_INST_STATUS<4>_UNCONNECTED , 
\NLW_clock16_generator/DCM_SP_INST_STATUS<3>_UNCONNECTED , \NLW_clock16_generator/DCM_SP_INST_STATUS<2>_UNCONNECTED , 
\NLW_clock16_generator/DCM_SP_INST_STATUS<1>_UNCONNECTED , \NLW_clock16_generator/DCM_SP_INST_STATUS<0>_UNCONNECTED })
  );
  IBUFG #(
    .CAPACITANCE ( "DONT_CARE" ),
    .IBUF_DELAY_VALUE ( "0" ),
    .IOSTANDARD ( "DEFAULT" ))
  \clock16_generator/CLKIN_IBUFG_INST  (
    .I(clock_in),
    .O(clock50_OBUF_11)
  );
  BUFG   \clock16_generator/CLKFX_BUFG_INST  (
    .I(\clock16_generator/CLKFX_BUF ),
    .O(clk16_OBUF_8)
  );
  LUT2 #(
    .INIT ( 4'h1 ))
  PS1_input1 (
    .I0(PS1),
    .I1(PS2),
    .O(PS1_input)
  );
  IBUF   reset_IBUF (
    .I(reset),
    .O(reset_IBUF_23)
  );
  OBUF   clock8_OBUF (
    .I(clock8_OBUF_13),
    .O(clock8)
  );
  OBUF   clock50_OBUF (
    .I(clock50_OBUF_11),
    .O(clock50)
  );
  OBUF   clk16_OBUF (
    .I(clk16_OBUF_8),
    .O(clk16)
  );
  OBUF   clock_PS1_OBUF (
    .I(clock_PS1_OBUF_15),
    .O(clock_PS1)
  );
  OBUF   clock_PS2_OBUF (
    .I(clock_PS2_OBUF_17),
    .O(clock_PS2)
  );
  OBUF   clock_PS3_OBUF (
    .I(clock_PS3_OBUF_19),
    .O(clock_PS3)
  );
  INV   CLK8_input1_INV_0 (
    .I(CLK8),
    .O(CLK8_input)
  );
endmodule


`ifndef GLBL
`define GLBL

`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire PRLD;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule

`endif

